Field of the Invention
The invention relates to an integrated memory having memory cells, which are arranged within a cell array along bit lines, word lines and at least two plate segments and each have a selection transistor and a storage capacitor, one electrode of each storage capacitor being connected via the associated selection transistor to one of the bit lines and another electrode being connected to one of the plate segments, and a control terminal of each selection transistor being connected to one of the word lines.
An integrated memory of this type in the form of an FRAM (Ferro-Electric Random Access Memory) is described in U.S. Pat. No. 5,373,463, which shows a first variant of an FRAM in which the plate segments are arranged parallel to the word lines, each plate segment being assigned to a word line. Another variant is shown, furthermore, in which plate segments run parallel to the bit lines, each plate segment being assigned to a bit line. The memories described in U.S. Pat. No. 5,373,463 operate according to the so-called "Pulsed plate concept". When information items are being written to or read from the memory cells, one of the word lines is activated, so that the associated selection transistors are switched on, and then the plate segment assigned to that memory cell which is intended to be accessed is brought firstly to a high supply potential and then to a low supply potential of the memory, that is to say is pulsed. Each access to one of the memory cells is thus connected with pulsing of the associated plate segment.
In ferroelectric memory cells, whose storage capacitors have a ferroelectric dielectric, aging phenomena such as the socalled "imprint" or the so-called "fatigue" occur and can lead to functional disturbances of the memory. Therefore, it is important, in the context of a memory test, to check whether the memory cells satisfy at least certain minimum requirements imposed on their resistance to aging. In order to check the aging effects, it is possible to carry out a large number of write and/or read accesses to each memory cell. Finally, the functionality of each cell is checked, so that it can be ascertained whether first defects rendering use of the memory impossible have already occurred on account of premature aging. Since today's memories have a multiplicity of memory cells, the above-described testing of the memory cells is very time-consuming.